[N-2-4] An 800V-class lateral NMOS structure with a reduced parasitic capacitance for a level-shift circuit integrated in a high voltage gate driver IC

M. Yamaji¹、A. Jonishi¹、H. Sumida¹、Y. Hashimoto² (1.Fuji Electric Corp. Ltd.、2.Shinshu Univ. (Japan))

https://doi.org/10.7567/SSDM.2014.N-2-4