[P-3-4] Impact of High-κ Spacers on Parasitic Effects Considering DC/AC Performance Optimization in Si-Nanowire FETs for sub 10 nm Technology Node

J.H. Hong¹, S.H. Lee¹, Y.R. Kim¹, E.Y. Jeong¹, J.S. Yoon¹, J.S. Lee¹, R.H. Baek², Y.H. Jeong¹ (1.Pohang Univ. of Tech. and Sci., 2.SEMATECH (Korea))

https://doi.org/10.7567/SSDM.2014.P-3-4