[PS-1-9] The Impact of Positive Bias Temperature Instabilities on Stacked High-k/Metal Gate Transistor with TiN Barrier Layer

D.C. Huang¹、J. Gong²、C.F. Huang¹、S.S. Chung³ (1.National Tsing Hua Univ.、2.Tunghai Univ.、3.NCTU (Taiwan))

https://doi.org/10.7567/SSDM.2014.PS-1-9