Effect of gate oxide process at SiC-MOS interface on threshold voltage shift analyzed by DLTS

J. Hasegawa; M. Noguchi; M. Furuhashi; S. Nakata; T. Iwasaki; T. Kodera; T. Nishimura; M. Hatano

doi:https://doi.org/10.7567/SSDM.2014.PS-14-13L

2014 International Conference on Solid State Devices and Materials

2014年9月8日〜 2014年9月11日
Tsukuba International Congress Center (EPOCHAL TSUKUBA), Ibaraki, Japan

[PS-14-13L] Effect of gate oxide process at SiC-MOS interface on threshold voltage shift analyzed by DLTS

J. Hasegawa¹、M. Noguchi²、M. Furuhashi²、S. Nakata²、T. Iwasaki¹、T. Kodera¹、T. Nishimura¹、M. Hatano¹ (1.Tokyo Inst. Of Tech.、2.Mitsubishi Electric Corp. (Japan))

https://doi.org/10.7567/SSDM.2014.PS-14-13L

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