The Japan Society of Applied Physics

09:00 〜 09:20

[F-6-1] 39% tAC Improvement, 11% Energy Reduction, 32Kbit 1R/1W 2port SRAM using Two-stage Read Boost and Write-Boost after Read Sensing Scheme

Y. Yamamoto1, S. Moriwaki1, A. Kawasumi2, S. Miyano3, H. Shinohara4 (1.Socionext Inc., 2.Toshiba Corp., 3.Previously with STARC, 4.Waseda Univ.(Japan))

https://doi.org/10.7567/SSDM.2015.F-6-1