2:30 PM - 2:50 PM

[K-1-2] Design of Complementary Raised-Drain Tunneling FET for Ultra-Low Voltage Applications

^○Y. B. Zhao¹, E. R. Hsieh¹, C. H. Chien¹, S. S. Chung¹ (1.National Chiao Tung Univ.(Taiwan))

https://doi.org/10.7567/SSDM.2015.K-1-2