Trench Gate Process for 60-nm-Node C-Axis Aligned Crystalline In-Ga-Zn-O Field-Effect Transistors

Y. Asami

doi:https://doi.org/10.7567/SSDM.2015.M-6-4

9:45 AM - 10:00 AM

[M-6-4] Trench Gate Process for 60-nm-Node C-Axis Aligned Crystalline In-Ga-Zn-O Field-Effect Transistors

^○Y. Asami¹, A. Shimomura¹, Y. Okazaki¹, D. Matsubayashi¹, M. Tsubuku¹, M. Kurata¹, S. Okamoto¹, S. Sasagwa¹, T. Moriwaka¹, T. Kakehata¹, Y. Yakubo¹, K. Kato¹, YamamotoY. ¹, S. Yamazaki¹ (1.Semiconductor Energy Laboratory Co., Ltd.(Japan))

https://doi.org/10.7567/SSDM.2015.M-6-4

2015 International Conference on Solid State Devices and Materials

[M-6-4] Trench Gate Process for 60-nm-Node C-Axis Aligned Crystalline In-Ga-Zn-O Field-Effect Transistors