(Invited) Annealing Techniques for Low Temperature Junctions Design in a 3D VLSI Integration

C. Fenouillet Beranger

doi:https://doi.org/10.7567/SSDM.2015.N-1-1

2:00 PM - 2:30 PM

[N-1-1] (Invited) Annealing Techniques for Low Temperature Junctions Design in a 3D VLSI Integration

C. Fenouillet Beranger¹, P. Batude¹, S. Kerdiles¹, B. Mathieu¹, P. Acosta Alba¹, L. Pasini^2,1, V. Lu^2,1, F. Deprat¹, L. Brunet¹, B. Sklenard¹, P. Rivallin¹, O. Rozeau¹, M-P. Samson^2,1, B. Previtali¹, L. Hortemel¹, N. Rambal^1,2, V. Lapras^1,2, M. Casse¹, S. Reboh¹, F. Piegas Luce¹, P. Besson¹, R. Kachtouli¹, A. Royer¹, D. Lafond¹, H. Dansas¹, F. Aussenac¹, J-P. Barnes¹, M. Vinet¹ (1.CEA-LETI, 2.STMicroelectronics(France))

https://doi.org/10.7567/SSDM.2015.N-1-1

2015 International Conference on Solid State Devices and Materials

[N-1-1] (Invited) Annealing Techniques for Low Temperature Junctions Design in a 3D VLSI Integration