5:25 PM - 5:55 PM

[N-5-1] (Invited) Engineering high-k/InGaAs Interface for Extremely Scaled Gate Stacks

^○D. H. Zadeh¹, H. Oomine², K. Kakushima², H. Iwai² (1.NTT Device Tech. Labs., 2.Tokyo Tech(Japan))

https://doi.org/10.7567/SSDM.2015.N-5-1