[PS-5-4] A Compact 0.3-to-1.125GHz Self-Biased PLL for System-on-Chip Clock Generation in 0.18μm CMOS

^○Z. Zhang¹, L. Liu¹, P. Feng¹, J. Liu¹, N. Wu¹ (1.Institute of Semiconductors, Chinese Academy of Sciences(China))

https://doi.org/10.7567/SSDM.2015.PS-5-4