The Japan Society of Applied Physics

[PS-5-4] A Compact 0.3-to-1.125GHz Self-Biased PLL for System-on-Chip Clock Generation in 0.18μm CMOS

Z. Zhang1, L. Liu1, P. Feng1, J. Liu1, N. Wu1 (1.Institute of Semiconductors, Chinese Academy of Sciences(China))

https://doi.org/10.7567/SSDM.2015.PS-5-4