The Japan Society of Applied Physics

3:00 PM - 3:15 PM

[N-1-06] Demonstration of a Common Gate-Stack Process for p-Ge and n-InGaAs CMOS Integration

P. Lee1, C. Chen1, S. Chang2, G. Luo2,J. Chyi1,3 (1.National Central Univ.(Taiwan), 2.National Nano Device Labs.(Taiwan), 3.Academia Sinica(Taiwan))

https://doi.org/10.7567/SSDM.2016.N-1-06