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[PS-3-03] Influence of Line-Edge Roughness (LER) on Multiple-Gate (MG) Tunnel Field-Effect Transistors (TFETs)

^○W. Y. Choi¹, S. H. Choi¹, J. W. Lee¹, I. Huh¹ (1.Sogang Univ.(Korea))

https://doi.org/10.7567/SSDM.2016.PS-3-03