16:50 〜 17:10

[E-2-04] Insights and Opportunities for Junctionless Gate-All-Around Lateral and Vertical Nanowire FETs

^○A. Veloso¹, P. Matagne¹, E. Simoen¹, A. Chasin¹, B. Kaczer¹, D. Yakimets¹, D. Mocuta¹, N. Collaert¹ (1.IMEC (Belgium))

https://doi.org/10.7567/SSDM.2017.E-2-04