10:20 〜 10:35

[E-5-03 (Late News)] Optimizing MOS-Gated Thyristor using Voltage-based Equivalent Circuit Model for Designing Steep Subthreshold Slope PN-Body Tied SOI FET

^○D. Ueda¹, K. Takeuchi¹, M. Kobayashi¹, T. Hiramoto¹ (1.Univ. of Tokyo (Japan))

https://doi.org/10.7567/SSDM.2017.E-5-03