[PS-3-05] Short Channel Modeling of Tunnel FET's ○K. Fukuda1, H. Asai1, J. Hattori1, T. Mori1, Y. Morita1, W. Mizubayashi1, M. Masahara1, S. Migita1, H. Ota1, K. Endo1, T. Matsukawa1 (1.AIST (Japan)) https://doi.org/10.7567/SSDM.2017.PS-3-05