[PS-3-06] Enhancement of Capacitance Benefit by Drain Offset Structure in TFET Circuit Speed Associated with Tunneling Probability Increase

^○H. Asai¹, T. Mori¹, T. Matsukawa¹, J. Hattori¹, K. Endo¹, K. Fukuda¹ (1.AIST (Japan))

https://doi.org/10.7567/SSDM.2017.PS-3-06