TCAD simulation of planar single-gate Si tunnel FET with average subthreshold swing less than 60 mV/dec for 0.3 V operation

K. Kukita

doi:https://doi.org/10.7567/SSDM.2017.PS-3-14

[PS-3-14 (Late News)] TCAD simulation of planar single-gate Si tunnel FET with average subthreshold swing less than 60 mV/dec for 0.3 V operation

^○K. Kukita¹, T. Uechi¹, J. Shimokawa¹, M. Goto¹, Y. Yokota¹, S. Kawanaka¹, T. Tanamoto², M. Koyama², H. Tanimoto¹, S. Takagi³ (1.Toshiba Memory Corp. (Japan), 2.Toshiba Corp. (Japan), 3.Univ. of Tokyo (Japan))

https://doi.org/10.7567/SSDM.2017.PS-3-14

2017 International Conference on Solid State Devices and Materials

[PS-3-14 (Late News)] TCAD simulation of planar single-gate Si tunnel FET with average subthreshold swing less than 60 mV/dec for 0.3 V operation