The Japan Society of Applied Physics

[PS-4-09] Impacts of Low Temperature formed SiO2 Tunneling and Si3N4/HfO2 Trapping Layers on Gate-All-Around Charge-Trapping Flash Memory Devices

P. -Y. Lin1, K. -S. Chang-Liao1, H. -K. Fang1, C. -H. Cheng1, W. -H. Huang2, C. -H. Shen2, J. -M. Shieh2 (1.National Tsing Hua Univ. (Taiwan), 2.National Nano Device Labs. (Taiwan))

https://doi.org/10.7567/SSDM.2017.PS-4-09