Impacts of Low Temperature formed SiO2 Tunneling and Si3N4/HfO2 Trapping Layers on Gate-All-Around Charge-Trapping Flash Memory Devices

P. -Y. Lin

doi:https://doi.org/10.7567/SSDM.2017.PS-4-09

[PS-4-09] Impacts of Low Temperature formed SiO₂ Tunneling and Si₃N₄/HfO₂ Trapping Layers on Gate-All-Around Charge-Trapping Flash Memory Devices

^○P. -Y. Lin¹, K. -S. Chang-Liao¹, H. -K. Fang¹, C. -H. Cheng¹, W. -H. Huang², C. -H. Shen², J. -M. Shieh² (1.National Tsing Hua Univ. (Taiwan), 2.National Nano Device Labs. (Taiwan))

https://doi.org/10.7567/SSDM.2017.PS-4-09

2017 International Conference on Solid State Devices and Materials

[PS-4-09] Impacts of Low Temperature formed SiO2 Tunneling and Si3N4/HfO2 Trapping Layers on Gate-All-Around Charge-Trapping Flash Memory Devices

[PS-4-09] Impacts of Low Temperature formed SiO₂ Tunneling and Si₃N₄/HfO₂ Trapping Layers on Gate-All-Around Charge-Trapping Flash Memory Devices