[PS-9-06] A Vertical Ge Tunneling FET With Tapered Source/Drain Strctures

K. Wu¹,^○G. -L. Luo¹, C. -L. Chu¹, S. -H. Chen¹, B. -Y. Chen¹, W. -F. Wu¹, W. -K. Yeh^1,2, C. -H. Chien³ (1.National Nano Device Labs. (Taiwan), 2.National Univ. of Kaohsiung (Taiwan), 3.National Chiao Tung Univ. (Taiwan))

https://doi.org/10.7567/SSDM.2017.PS-9-06