2:45 PM - 3:00 PM

[C-1-03] Challenges and Opportunities for Vertical Nanowire FETs: Device Design and Fabrication

^○A. Veloso¹, P. Matagne¹, T. Huynh-Bao¹, G. Eneman¹, R. Loo¹, K. Wostyn¹, S. Brus¹, J. Boemmels¹, D. Mocuta¹, J. Ryckaert¹ (1.Imec (Belgium))

https://doi.org/10.7567/SSDM.2018.C-1-03