Mitigating Edge Effects In Gate-Normal Tunneling Feld-Effect Transistors Using a Ti/TiN Dual-Metal Gate

S. Glass

doi:https://doi.org/10.7567/SSDM.2018.C-7-06

10:15 AM - 10:30 AM

[C-7-06] Mitigating Edge Effects In Gate-Normal Tunneling Feld-Effect Transistors Using a Ti/TiN Dual-Metal Gate

S. Glass¹,^○M. Liu¹, K. Kato², J.-M. Hartmann³, S. Takagi², D. Buca¹, S. Mantl¹, Q.-T. Zhao¹ (1.Res. Center Juelich (Germany), 2.Univ. of Tokyo (Japan), 3.Univ. of Grenoble and CEA, LETI (France))

https://doi.org/10.7567/SSDM.2018.C-7-06

2018 International Conference on Solid State Devices and Materials

[C-7-06] Mitigating Edge Effects In Gate-Normal Tunneling Feld-Effect Transistors Using a Ti/TiN Dual-Metal Gate