3:00 PM - 3:15 PM

[D-1-04] A Compact Model of MOS Capacitors Taking Deep Level Trap Effects into Account

^○K. Fukuda¹, H. Asai¹, J. Hattori¹, M. Shimizu¹, T. Hashizume² (1.AIST (Japan), 2.Hokkaido Univ. (Japan))

https://doi.org/10.7567/SSDM.2018.D-1-04