14:15 〜 14:30

[D-8-02] Double RESURF JTEs Structure for Low On-Resistance Trench Gate SiC MOSFET

^○Y. Saitoh¹, T. Masuda¹, H. Michikoshi¹, H. Shiomi¹, S. Harada¹, Y. Mikamura² (1.AIST (Japan), 2.Sumitomo Electric Industries, Ltd. (Japan))

https://doi.org/10.7567/SSDM.2018.D-8-02