CMOS Area Scaling And the Need for High Aspect Ratio Vias

B. Briggs

doi:https://doi.org/10.7567/SSDM.2018.G-3-02

09:30 〜 09:45

[G-3-02] CMOS Area Scaling And the Need for High Aspect Ratio Vias

^○B. Briggs¹, S. Guissi², C.J. Wilson¹, J. Ryckaert¹, S. Paolillo¹, K. Vandersmissen¹, J. Versluijs¹, C. Lorant¹, N. Heylen¹, J. Boemmels¹, Z. Tokei¹, Y. Sherazi¹, P. Weckx¹, L. Kljucar¹, M. Van Der Veen¹, G. Boccardi¹, V. DeHeyn¹, A. Gupta¹, J. Ervin³, M. Kamon³ (1.imec (Belgium), 2.Coventor (France), 3.Coventor Inc (USA))

https://doi.org/10.7567/SSDM.2018.G-3-02

2018 International Conference on Solid State Devices and Materials

[G-3-02] CMOS Area Scaling And the Need for High Aspect Ratio Vias