p-MoS2/HfS2 van der Waals Heterostructure Transistor Using Ni Backgate Buried in HfO2 Dielectric

W. Zhang

doi:https://doi.org/10.7567/SSDM.2018.M-7-04

9:30 AM - 9:45 AM

[M-7-03] p-MoS₂/HfS₂ van der Waals Heterostructure Transistor Using Ni Backgate Buried in HfO₂ Dielectric

^○W. Zhang¹, S. Netsu¹, T. Kanazawa¹, T. Amemiya², Y. Miyamoto¹ (1.Dept. Electrical and Electronic Engineering, Tokyo Tech (Japan), 2.IIR, Tokyo Tech (Japan))

https://doi.org/10.7567/SSDM.2018.M-7-04

2018 International Conference on Solid State Devices and Materials

[M-7-03] p-MoS2/HfS2 van der Waals Heterostructure Transistor Using Ni Backgate Buried in HfO2 Dielectric

[M-7-03] p-MoS₂/HfS₂ van der Waals Heterostructure Transistor Using Ni Backgate Buried in HfO₂ Dielectric