9:30 AM - 9:45 AM

[N-7-03] Mechanism of Threshold Voltage Control by Back Gates in CAAC-IGZO FETs

^○R. Honda¹, K. Tsuda¹, T. Takeuchi¹, K. Tochibayashi¹, T. Atsumi¹, K. Kato¹, S. Yamazaki¹ (1.Semiconductor Energy Laboratory Co., Ltd. (Japan))

https://doi.org/10.7567/SSDM.2018.N-7-03