3:15 PM - 3:30 PM

[N-1-05 (Late News)] Evaluation of 2D Negative-Capacitance FET Based Subsystem-Level Logic Circuits Considering Ferroelectric Nonuniformity

^○Y.J. Wu¹, W.X. You¹, P. Su¹ (1.NCTU (Taiwan))

https://doi.org/10.7567/SSDM.2019.N-1-05