4:00 PM - 4:15 PM
[N-4-02] Bottom Tier High Voltage Vevice Thermal Stability in 3D Sequential Integration for More than Moore Applications
○C. Cavalcante1,2,3, G. Ghibaudo2, X. Garros1, M. Cassé1, T. Karatsori2, J. Lacord1, C. Fenouillet1, N. Rambal1, O. Rozeau1, J.P. Colinge1, M. Vinet1, D. Lattard1, F. Andrieu1, P. Batude1
(1.Lab. CEA-LETI, MINATEC (France), 2.Inst. IMEP-LAHC, Grenoble INP (France), 3.Univ. Grenoble Alpes (France))
https://doi.org/10.7567/SSDM.2019.N-4-02