A Fast-Locking All-Digital PLL with Dynamic Loop Gain Control and Phase Self-Alignment Mechanism for Sub-GHz IoT Applications

1:00 PM - 3:00 PM

[PS-SP-03] A Fast-Locking All-Digital PLL with Dynamic Loop Gain Control and Phase Self-Alignment Mechanism for Sub-GHz IoT Applications

^○H.H. Wang¹, Y.L. Lo¹, W.B. Yang² (1.National Kaohsiung Normal Univ. (Taiwan), 2.Tamkang Univ. (Taiwan))