13:00 〜 15:00
[PS-SP-03] A Fast-Locking All-Digital PLL with Dynamic Loop Gain Control and Phase Self-Alignment Mechanism for Sub-GHz IoT Applications
○H.H. Wang1, Y.L. Lo1, W.B. Yang2
(1.National Kaohsiung Normal Univ. (Taiwan), 2.Tamkang Univ. (Taiwan))
https://doi.org/10.7567/SSDM.2019.PS-SP-03