Design of an Energy-Efficient Binarized Convolutional Neural Network Accelerator Using a Nonvolatile FPGA with Only-Once-Write Shifting

11:30 〜 11:45

[B-8-03] Design of an Energy-Efficient Binarized Convolutional Neural Network Accelerator Using a Nonvolatile FPGA with Only-Once-Write Shifting

〇Daisuke Suzuki¹, Takahiro Oka², Takahiro Hanyu² (1. The University of Aizu(Japan), 2. Tohoku Univ.(Japan))