[20a-E301-1~12] 13.7 Compound and power electron devices and process technology

[20a-E301-6] CV, DLTS of SiO₂/p-GaN MOS fabricated on high-temperature annealed p-GaN

〇(M1)Hikaru Yoshida¹, Wakana Takeuchi¹, Yutaka Tokuda¹, Takashi Okawa², Hidemoto Tomita² (1.Aichi Inst. of Technol., 2.Toyota Motor Corporation)

Keywords:p-GaN

We studied the effect of high temperature annealing on Mg-doped p-GaN grown by MOVPE. The GaN sample was p⁺ (8x10¹⁹ cm^-3)/p (1x10¹⁸ cm-³)/n^-/n⁺-GaN substrate. The SiO₂/p-GaN MOS was fabricated on the GaN sample annealed at 1142 °C for 5 min. The characterization of the SiO₂/p-GaN MOS was performed by CV and DLTS measurements. Ionized acceptor concentration was found to be decreased to 6.5x10¹⁶ cm^-3 in the p⁺ layer by annealing at 1142 °C. One sharp peak was observed as a bulk trap at 355 K in the DLTS spectrum with the time constant of 191 ms. The broad DLTS spectra with one peak around 350 K appeared when using the bias pulse to measure both the interface states and bulk traps.