[15a-A305-1~13] 13.3 絶縁膜技術

▲ [15a-A305-12] Comparison of carrier trap characteristics in different interfacial layers of n-Ge MOS structures

〇Mengnan Ke¹、Mitsuru Takenaka¹、Shinichi Takagi¹ (1.Univ. Tokyo)

キーワード：Ge, MOS interfaces

One of the key technologies for realizing Ge CMOS is the formation of gate stacks with low defect densities. (HfO₂)/Al₂O₃/GeO_x/Ge interfaces realized by post plasma oxidation (post-PO) are promising for reducing interface states density. However, a remaining critical issue is the existence of a large amount of slow traps, which can be an inherent problem for Ge gate stacks. It has been reported that Y-doped GeO_x interfaces and Al₂O₃/GeO_x/Ge formed by pre plasma oxidation (pre-PO) can reduce slow trap density (N_st). However, reduction in N_st is not sufficient yet, particularly for electrons. Thus, understanding of physical origins of the slow electron traps and the carrier trapping properties is strongly required to establish a guideline for further reduction in N_st and a method of the oxide reliability prediction for Ge MOS interfaces. We have proposed a new measurement to discriminate existing and generated electron slow traps. It has been found that only existing slow traps are responsible in low E_ox, while generation of slow traps and hole trapping additionally occur in high E_ox. In this study, we compare the existing electron, generated electron and hole trap density of n-Ge MOS interfaces with different interfacial layers including Y₂O₃ under electrical stress by utilizing the above technique.