[19a-C10-1~9] 13.4 Interconnection technology

△ [19a-C10-9] Effect of Chip Thinning Process on DRAM Retention Time in 3D IC

^○(M2)Seiya Tanikawa¹, Hideki Naganuma¹, Takaharu Tani¹, Hisashi Kino¹, Jicheol Bea², Takafumi Fukushima², Kang-Wook Lee², Mitsumasa Koyanagi², Tetsu Tanaka^1,3 (Dept. of Bioengineering and Robotics, Tohoku Univ.¹, New Industry Creation Hatchery Center (NICHe),², Dept. of Biomedical Engineering, Tohoku Univ.³)

Keywords:三次元集積化技術