[20a-C8-1~12] 13.6 Silicon devices / Integration technology

[20a-C8-6] Floating Gate Memory with Three-Dimensional Nanodot Array Formed by Bio-Layer-by-Layer Method

^○Hiroki Kamitake^1,2, Mutsunori Uenuma², Yasuaki Ishikawa^1,2, Ichiro Yamashita^1,2, Yukiharu Uraoka^1,2 (NAIST¹, CREST²)

Keywords:フローティングゲートメモリ,ナノドット,Dps