Poster presentation

[18p-P10-1~13] 13.6 Silicon devices / Integration technology

Wed. Sep 18, 2013 1:30 PM - 3:30 PM P10 (Davis Memorial Auditorium)

△：Young Scientist Oral Presentation Award Applied
▲：English Presentation
▼：Both Award Applied and English Presentation

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1:30 PM - 3:30 PM

[18p-P10-1] Si/SiGe Hole-Tunneling Asymmetric-Double-Quantum-Well RTD

^○Yuki Maeda¹, Takahiro Tsukamoto¹, Yoshiyuki Suda¹ (Tokyo Univ. of Agric. & Technol.¹)

1:30 PM - 3:30 PM

△ [18p-P10-2] Ultra-thin body Ge-on insulator nMOSFETs fabricated by Ge condensation and Sb diffusion

^○(M2)WuKang Kim¹, Yufei Kin¹, Younghyun Kim¹, SangHyeon Kim¹, Takenori Osada², Masahiko Hata², Mitsuru Takenka¹, Shinichi Takagi¹ (The University of Tokyo¹, Sumitomo Chemical Co. Ltd.²)

1:30 PM - 3:30 PM

[18p-P10-3] GeSn pMOSFETs on Si (111) by solid phase epitaxy

^○Tatsuro maeda¹, Jevasuwan Wipakorn¹, Hiroyuki Hattori¹, Noriyuki Uchida¹, J. -P. Locquet², R. R. Lieten^{2, 3} (AIST¹, KU Leuven², IMEC³)

1:30 PM - 3:30 PM

[18p-P10-4] Poly Germanium Junctionless Tri-gate FET for 3-D Stacked IC

Yoshiki Kamata¹, ^○Yuuichi Kamimuta¹, Keiji Ikeda¹, Kiyoe Furuse¹, Mizuki Ono¹, Minoru Oda¹, Yoshihiko Moriyama¹, Kouji Usuda¹, Masahiro Koike¹, Toshifumi Irisawa¹, Etsuo Kurosawa¹, Tsutomu Tezuka¹ (AIST GNC¹)

1:30 PM - 3:30 PM

[18p-P10-5] Enhancement of Hole Mobility and Cut-off Characteristics of Strained Ge Nanowire pMOSFETs by using Plasma Oxidized GeOx Inter-layer for Gate Stack

^○Keiji Ikeda¹, Yuuichi Kamimuta¹, Yoshihiko Moriyama¹, Mizuki Ono¹, Koji Usuda¹, Minoru Oda¹, Toshifumi Irisawa¹, Kiyoe Furuse¹, Tsutomu Tezuka¹ (AIST-GNC¹)

1:30 PM - 3:30 PM

[18p-P10-6] Demonstration of high mobility InGaAs/Ge CMOS using stacked 3D integration

^○Toshifumi Irisawa¹, Minoru Oda¹, Yuuichi Kamimuta¹, Yoshihiko Moriyama¹, Keiji Ikeda¹, Eiko Mieda¹, Jevaswan Wipakorn¹, Tatsurou Maeda¹, Osamu Ichikawa², Takenori Osada², Masahiko Hata², Tsutomu Tezuka¹ (AIST-GNC¹, Sumitomo Cemical Co. Ltd²)

1:30 PM - 3:30 PM

[18p-P10-7] Gate-first process and EOT-scaling of III-V nanowire-channels on Si

^○Katsuhiro Tomioka^1,2, Masatoshi Yoshimura¹, Takashi Fukui¹ (GS-IST, RCIQE, Hokkaido Univ.¹, JST-PRESTO²)

1:30 PM - 3:30 PM

[18p-P10-8] BSIM4 Parameter Extraction for Tri-gate Si Nanowire Transistors

^○Chika Tanaka¹, Masumi Saitoh¹, Kensuke Ota¹, Toshinori Numata¹, Daisuke Matsushita¹ (Corporate R&D Center, Toshiba Corporation¹)

1:30 PM - 3:30 PM

[18p-P10-9] Low-dielectric constant SiCN charge trapping layer for nonvolatile memory applications

^○Shinji Naito¹, Shuichi Nakiri², Yoshina Ito², Hironobu Shiraiwa², Kiyoteru Kobayashi^1,2 (Graduate School of Engineering, Tokai Univ.¹, Tokai Univ.²)

1:30 PM - 3:30 PM

[18p-P10-10] Investigation of Traps in Insulator Films of MOSFET by Means of Isochronal Annealing Techniques

^○Ichiro Yamakawa¹, Yoshiki Yonamoto¹ (YRL, Hitachi, Ltd.¹)

1:30 PM - 3:30 PM

[18p-P10-11] On-Chip Dipole Antennas for Inter-Chip Signal Transmission

^○(M1)Kenji Hashimoto¹, Takumi Sugitani¹, Shinichi Kubota¹, Takamaro Kikkawa¹ (Hiroshima Univ. Nano device Inst.¹)

1:30 PM - 3:30 PM

[18p-P10-12] UWB Characteristics of On-Chip Inductors

^○(M1)Mitian Wang¹, Azhari Afreen¹, kenta Sogo¹, Takamaro Kikkawa¹ (Hiroshima Univ.Nano device Inst.¹)

1:30 PM - 3:30 PM

▲ [18p-P10-13] A DC-27 GHz -30 dB Isolation Tx/Rx Single Pole Double Throw (SPDT) Switch for Gaussian Monocycle Pulse Transmission

^○Azhari Afreen¹, Kenta Sogo¹, Mitian Wang¹, Akihiro Toya¹, Takamaro Kikkawa¹ (Hiroshima Univ.¹)

Oral presentation

[19a-C8-1~12] 13.6 Silicon devices / Integration technology

Thu. Sep 19, 2013 9:00 AM - 12:15 PM C8 (TC3 2F-201)

△：Young Scientist Oral Presentation Award Applied
▲：English Presentation
▼：Both Award Applied and English Presentation

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9:00 AM - 9:15 AM

[19a-C8-1] [Young Scientist Oral Presentation Award Speech](15 min.) Drain-Current Fluctuation during Dynamic Gate Bias in Si MOSFETs due to Random Telegraph Noise

^○Wei Feng^1,2, Keisaku Yamada^1,2, Kenji Ohmori^1,2 (Univ. of Tsukuba¹, JST-CREST²)

9:15 AM - 9:30 AM

[19a-C8-2] Analysis of Multi-Trap Random Telegraph Noise Using Trap Charging History (I):Judgment of the Number and Charging Conditions of the Oxide Traps

^○Toshiaki Tsuchiya¹, Naoyoshi Tamura², Akihito Sakakidani², Kenichiro Sonoda², Masayuki Kamei², Shinya Yamakawa², Sumio Kuwabara² (Shimane Univ.¹, STARC²)

9:30 AM - 9:45 AM

[19a-C8-3] Analysis of Multi-Trap Random Telegraph Noise Using Trap Charging History (II):Characterization of Each Individual Oxide Trap

^○Toshiaki Tsuchiya¹, Naoyoshi Tamura², Akihito Sakakidani², Kenichiro Sonoda², Masayuki Kamei², Shinya Yamakawa², Sumio Kuwabara² (Shimane Univ.¹, STARC²)

9:45 AM - 10:00 AM

△ [19a-C8-4] A Study on Strain Induced Random Telegraph Noise Suppression in pMOSFETs

^○JIEZHI CHEN¹, Yusuke Higashi¹, Izumi Hirano¹, Yuichiro Mitani¹ (Toshiba R&D Center¹)

10:00 AM - 10:15 AM

△ [19a-C8-5] Dependence of soft error rate in SOI SRAM on generated charge under buried oxide by high energy ion probes

^○Masatoshi Hazama¹, Satoshi Abo¹, Fujio Wakaya¹, Takahiro Makino², Shinobu Onoda², Takeshi Ohshima², Toshiaki Iwamatsu³, Hidekazu Oda³, Mikio Takai¹ (CQSTEC¹, JAEA², Renesas Electronics Corp.³)

Break （10:15 AM - 10:30 AM）

10:30 AM - 10:45 AM

[19a-C8-6] Analysis of current-onset voltage fluctuation for FinFETs : Influence of work function variation of metal gates

^○Takashi Matsukawa¹, Yongxun Liu¹, Junichi Tsukada¹, Kazuhiko Endo¹, Hiromi Yamauchi¹, Yuki Ishikawa¹, Shinichi O'uchi¹, Wataru Mizubayashi¹, Hiroyuki Ota¹, Shinji Migita¹, Yukinori Morita¹, Meishoku Masahara¹ (AIST¹)

10:45 AM - 11:00 AM

[19a-C8-7] Reconsideration of the Threshold Voltage Variability Estimated with Pair Transistor Cell Array

^○Kazuo Terada¹, Katsuhiro Tsuji¹ (Hiroshima City Univ.¹)

11:00 AM - 11:15 AM

▲ [19a-C8-8] Recovery Behaviors of |Vth| Shift of pFETs by High-Voltage OFF-State and ON-State Stress for Post-Fabrication SRAM Cell Stability Self-Improvement

^○Nurul Ezaila Alias¹, Anil Kumar¹, Takuya Saraya¹, Shinji Miyano², Toshiro Hiramoto¹ (IIS, Univ. of Tokyo¹, STARC²)

11:15 AM - 11:30 AM

[19a-C8-9] Reduced Cell Current Variability in Fully Depleted Silicon-on-Thin-BOX (SOTB) SRAM Cells at Supply Voltage of 0.4V

^○Tomoko Mizutani¹, Yoshiki Yamamoto², Hideki Makiyama², Hirofumi Shinohara², Toshiaki Iwamatsu², Hidekazu Oda², Nobuyuki Sugii², Toshiro Hiramoto¹ (IIS, Univ. of Tokyo¹, LEAP²)

11:30 AM - 11:45 AM

▲ [19a-C8-10] Performance Degradation Due to Drain-Induced Barrier Lowering in Ultra-Low Supply Voltage CMOS Circuits Operating in Subthreshold Region

^○SeungMin Jung¹, Tomoko Mizutani¹, Toshiro Hiramoto¹ (IIS, Univ. of Tokyo¹)

11:45 AM - 12:00 PM

[19a-C8-11] Analysis of Drain Voltage Dependence of Drain Induced Barrier Lowering (DIBL)

^○Mitsuaki Mitsuaki¹, Tomoko Mizutani¹, Toshiro Hiramoto¹ (IIS, Univ. of Tokyo¹)

12:00 PM - 12:15 PM

[19a-C8-12] SRAM Cell Stability Parameter: Noise Margin or Vmin?

^○Anil Kumar¹, Takuya Saraya¹, Shinji Miyano², Toshiro Hiramoto¹ (IIS, Univ. of Tokyo¹, STARC²)

Oral presentation

[19p-C8-1~18] 13.6 Silicon devices / Integration technology

Thu. Sep 19, 2013 1:15 PM - 6:30 PM C8 (TC3 2F-201)

△：Young Scientist Oral Presentation Award Applied
▲：English Presentation
▼：Both Award Applied and English Presentation

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Lunch （12:15 PM - 1:15 PM）

1:15 PM - 1:45 PM

[19p-C8-1] [JSAP Paper Award Speech](30 min.) Single-Electron Stochastic Resonance Using Si Nanowire Transistors

^○Katsuhiko Nishiguchi¹, Akira Fujiwara¹ (NTT BRL¹)

1:45 PM - 2:00 PM

△ [19p-C8-2] Characterization of MOS Si/SiGe quantum point contact

^○Jun Kamioka¹, Tetsuo Kodera^1,2,3, Kenta Takeda⁴, Toshiaki Obata⁴, Waseem. M. Akhtar⁴, Seigo Tarucha^2,4,5, Shunri Oda¹ (QNERC, Tokyo Tech.¹, NanoQuine, the Univ. of Tokyo², PRESTO-JST³, The Univ. of Tokyo⁴, RIKEN⁵)

2:00 PM - 2:15 PM

△ [19p-C8-3] Characterization of p-Channel Si Double Quantum Dot by Hole Transport

^○Ko Yamada¹, Tetsuo Kodera^1,2,3, Tomohiro Kambara¹, Yukio Kawano¹, Shunri Oda¹ (QNERC, Tokyo Tech.¹, NanoQuine, Univ. of Tokyo², JST-PRESTO³)

2:15 PM - 2:30 PM

△ [19p-C8-4] Observation of the excitation of electrons in silicon quantum dots generated from the back-action of a charge sensor

^○Kosuke Horibe¹, Tetsuo Kodera^1,2,3, Yukio Kawano¹, Shunri Oda¹ (QNERC, Tokyo Tech.¹, NanoQuine, the Univ. of Tokyo², PRESTO-JST³)

2:30 PM - 2:45 PM

△ [19p-C8-5] Charge sensing of a silicon triangular triple quantum dot system

^○(M2)Raisei Mizokuchi¹, Tetsuo Kodera^1,2,3, Kosuke Horibe¹, Yukio Kawano¹, Yasuhiko Arakawa^2,4, Shunri Oda¹ (QNERC, Tokyo Tech.¹, NanoQuine, the Univ. of Tokyo², PRESTO-JST³, IIS, the Univ. of Tokyo⁴)

2:45 PM - 3:00 PM

[19p-C8-6] The characteristics of Excited states of double-gate Si single-electron transistor

^○Isamu Yoshioka¹, Takafumi Uchida¹, Hikaru Satou¹, Masashi Arita¹, Satoshi Fujiwara², Yasuo Takahashi¹ (IST. Hokkaido Univ.¹, NTT Basic Research Labs.²)

3:00 PM - 3:15 PM

[19p-C8-7] The change of the capacitive coupling of double quantum dot Si single-electron transistor in few electron regime

^○(M2)Takafumi Uchida¹, Isamu Yoshioka¹, Masashi Arita¹, Akira Fujiwara², Yasuo Takahashi¹ (IST. Hokkaido Univ¹, NTT Basic Research Labs²)

Break （3:15 PM - 3:30 PM）

3:30 PM - 4:00 PM

[19p-C8-8] [Award for Best Review Paper Speech](30 min.)Current Status and Future Perspective in Post-Scaling Technology

^○Shigeaki Zaima¹ (Nagoya Univ.¹)

4:00 PM - 4:15 PM

[19p-C8-9] Experimental Study on 2D-Si Layers for Future Several-nm CMOS (III)

^○Yuusuke Nagata¹, Yuuta Makahara¹, Yuuya Suzuki¹, Takashi Aoki¹, Toshiyuki Samejima², Tomohirsa Mizuno¹ (Kanagawa Univ.¹, Tokyo Univ. Agri. Tech.²)

4:15 PM - 4:30 PM

[19p-C8-10] Experimental Study on 2D-Si Layers for Future Several-nm CMOS (IV)

^○Yuya Suzuki¹, Yuta Nakahara¹, Yusuke Nagata¹, Takashi Aoki¹, Tomohisa Mizuno¹, Toshiyuki Samezima² (Kanagawa Univ.¹, Tokyo Univ. Agri. Tech.²)

4:30 PM - 4:45 PM

[19p-C8-11] Experimental Study on 2D-Si layers for Future Several-nm CMOS (V)

^○Yuta Nakahara¹, Yusuke Nagata¹, Yuya Suzuki¹, Takashi Aoki¹, Toshiyuki Sameshima², Tomohisa Mizuno¹ (Kanagawa Univ.¹, Tokyo Univ. Agri. Tech.²)

4:45 PM - 5:00 PM

△ [19p-C8-12] Low temperature formation of Ni-GaSb alloy Schottky junction for Metal Source/Drain of GaSb pMOSFET

^○Koichi Nishi¹, SangHyoen Kim¹, Masahumi Yokoyama¹, Haruki Yokoyama², Mituru Takenaka¹, Shinichi Takagi¹ (University of Tokyo¹, NTT Photonics Laboratories, NTT Corporation²)

5:00 PM - 5:15 PM

△ [19p-C8-13] Channel Length Scaling Limits of III-V Channel MOSFETs Governed By Source-Drain Direct Tunneling

^○(M1)Masaki Ohmori¹, Shunsuke Koba¹, Yōsuke Maegawa¹, Hideaki Tsuchiya^1,3, Yoshinari Kamakura^2,3, Nobuya Mori^2,3, Matsuto Ogawa¹ (Kobe Univ.¹, Osaka Univ.², JST CREST³)

5:15 PM - 5:30 PM

[19p-C8-14] Performance Prediction on n-MOSFET using Single-Layer MoS₂ Channel

^○Takumi Ohashi¹, Hitoshi Wakabayashi², Kuniyuki Kakushima², Nobuyuki Sugii², Akira Nishiyama², Yoshinori Kataoka², Kenji Natori³, Kazuo Tsutsui², Hiroshi Iwai³ (Tokyo Tech. ENG¹, Tokyo Tech. IGSSE², Tokyo Tech. FRC³)

5:30 PM - 5:45 PM

[19p-C8-15] Effect of Ionization Energy Increase of Phosphorus Dopants in Nanwire Transistors’s Electrical characterizations

^○Yuya Kurosawa^1,2, Naoya Kadotani¹, Tunaki Takahashi², Teruyuki Ohashi¹, Shunri Oda³, Ken Uchida^1,2 (Dept. Phys. Elec Tokyo Institute of Technology.¹, Keio Univ.², QNERC Tokyo Institute of Technology³)

5:45 PM - 6:00 PM

[19p-C8-16] Effect of Deformation Potential Increase at MOS Interfaces on Drain Current of Ultrathin Channel MOSFETs

^○Shunsuke Koba¹, Ryoma Ishida¹, Yuko Kubota¹, Hideaki Tsuchiya^1,3, Yoshinari Kamakura^2,3, Nobuya Mori^2,3, Matsuto Ogawa¹ (Kobe Univ.¹, Osaka Univ.², JST CREST³)

6:00 PM - 6:15 PM

[19p-C8-17] Extraction of Quasi-Ballistic Transport Parameters in Ultrashort Channel Si MOSFETs

^○Ryoma Ishida¹, Shunsuke Koba¹, Hideaki Tsuchiya^1,3, Yoshinari Kamakura^2,3, Nobuya Mori^2,3, Matsuto Ogawa¹ (Kobe Univ.¹, Osaka Univ.², JST CREST³)

6:15 PM - 6:30 PM

[19p-C8-18] Performance Enhancement of Schottky Barrier Tunnel FET with Core-Shell Gate Structure

^○Shuichiro Hashimoto¹, Yasuhiro Shikahama¹, Takanobu Watanabe^1,2 (Waseda Univ.¹, Waseda INN.²)

Oral presentation

[20a-C8-1~12] 13.6 Silicon devices / Integration technology

Fri. Sep 20, 2013 9:00 AM - 12:15 PM C8 (TC3 2F-201)

△：Young Scientist Oral Presentation Award Applied
▲：English Presentation
▼：Both Award Applied and English Presentation

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9:00 AM - 9:15 AM

[20a-C8-1] Contact Hole Fabrication Using Directed Self-Assembly Lithography

^○Ayako Kawanishi¹, Yuriko Seino¹, Masahiro Kanno¹, Hirokazu Kato¹, Hironobu Sato¹, Katsutoshi Kobayashi¹, Hiroki Yonemitsu¹, Mitsuhiro Omura¹, Yusuke Kasahara¹, Tsubasa Imamura¹, Noriko Sakurai¹, Tsukasa Azuma¹ (Toshiba corporation¹)

9:15 AM - 9:30 AM

[20a-C8-2] Investigation of Scaling Law for Cosmic-ray Neutron Induced Multiple Cell Upsets

Kenshiro Sakuta¹, ^○Shin-ichiro Abe^1,2, Yukinobu Watanabe¹, Ryo Harada³, Masanori Hashimoto³, Hiroshi Fuketa⁴, Taiki Uemura⁵ (Kyushu Univ.¹, JSPS Research Fellow², Osaka Univ.³, IIS, Univ. of Tokyo⁴, Fujitsu Semiconductor Ltd.⁵)

9:30 AM - 9:45 AM

△ [20a-C8-3] Investigation of Mechanical-Stress Reduction in 3D IC with Room Temperature Curing Adhesive

^○Hisashi Kino¹, Takafumi Fukusima², Mitsumasa Koyanagi², Tetsu Tanaka^1,3 (Tohoku Univ.¹, Tohoku Univ.², Tohoku Univ.³)

9:45 AM - 10:00 AM

[20a-C8-4] Novel Optoelectronic Power Amplifier Composed of Si Solar Cell and LED

^○Kensho Okamoto¹, Junichi Fujita¹, Tetsuo Hattori¹ (Kagawa Univ.¹)

10:00 AM - 10:15 AM

[20a-C8-5] Humidity Testing of Eternal Memory “Digital Rosetta Stone”

^○Taketoshi Matsumoto¹, Tomoki Akai¹, Shigeki Imai¹, Hikaru Kobayashi¹ (ISIR, Osaka Univ., CREST-JST¹)

10:15 AM - 10:30 AM

[20a-C8-6] Floating Gate Memory with Three-Dimensional Nanodot Array Formed by Bio-Layer-by-Layer Method

^○Hiroki Kamitake^1,2, Mutsunori Uenuma², Yasuaki Ishikawa^1,2, Ichiro Yamashita^1,2, Yukiharu Uraoka^1,2 (NAIST¹, CREST²)

Break （10:30 AM - 10:45 AM）

10:45 AM - 11:00 AM

[20a-C8-7] Gate structure dependence of electrical characteristics in floating-gate type poly-Si channel FinFET flash memories

^○Yongxun Liu¹, Takashi Matsukawa¹, Kazuhiko Endo¹, Shinichi Ouchi¹, Junichi Tsukada¹, Hiromi Yamauchi¹, Yuki Ishikawa¹, Wataru Mizubayashi¹, Yukinori Morita¹, Shinji Migita¹, Hiroyuki Ota¹, Meishoku Masahara¹ (AIST¹)

11:00 AM - 11:15 AM

[20a-C8-8] Comparative study of electrical characteristics for TiN metal and poly-Si gated charge trapping type FinFET flash memories

11:15 AM - 11:30 AM

▲ [20a-C8-9] Analysis of Photoresponse in SOI FinFET

^○(D)Dedy Putranto^1,3, Kazuhiko Endo², Meishoku Masahara², Hiroaki Satoh¹, Atsushi Ono¹, Purnomo Priambodo³, Djoko Hartanto³, Hiroshi Inokawa¹ (Res. Inst. of Electron., Shizuoka Univ.¹, Nanoelectron. Res. Inst., Nat. Inst. of Adv. Ind. Sci. & Technol.², Electrical Eng. Dept., Univ. of Indonesia³)

11:30 AM - 11:45 AM

[20a-C8-10] Methodology for Evaluating Operation Temperature of FinFETs in a Circuit

^○(P)Tsunaki Takahashi¹, Shunri Oda², Ken Uchida¹ (Keio Univ.¹, Tokyo Inst. Tech.²)

11:45 AM - 12:00 PM

[20a-C8-11] Mechanism of Recovery from Negative Bias Temperature Instability

^○Yoshiki Yonamoto¹ (Hitachi, Ltd., Yokohama Laboratory¹)

12:00 PM - 12:15 PM

[20a-C8-12] Estimation of Effective Channel Length from MOSFET C-V Curve Measured by Charge-Based Capacitance Measurement

^○Katsuhiro Tsuji¹, Kazuo Terada¹ (Hiroshima City Univ.¹)

Oral presentation

[20p-C8-1~5] 13.6 Silicon devices / Integration technology

Fri. Sep 20, 2013 1:15 PM - 2:30 PM C8 (TC3 2F-201)

△：Young Scientist Oral Presentation Award Applied
▲：English Presentation
▼：Both Award Applied and English Presentation

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Lunch （12:15 PM - 1:15 PM）

1:15 PM - 1:30 PM

▲ [20p-C8-1] KFM Measurement of Nano-Scale Selectively Doped Silicon Channel

^○Krzysztof Tyszka^1,2, Daniel Moraru¹, Takeshi Mizuno¹, Ryszard Jablonski², Michiharu Tabe¹ (Shizuoka Univ.¹, Warsaw Univ. Technol.²)

1:30 PM - 1:45 PM

▲ [20p-C8-2] Transport Spectroscopy of Dopant States in Randomly-Doped Single-Electron Transistors

^○(PC)Arup Samanta¹, Daniel Moraru¹, Earfan Hamid¹, Yohei Kuzuya¹, Lee The Anh², Takeshi Mizuno¹, Hiroshi Mizuta^2,3, Michiharu Tabe¹ (Reaserch Inst. of Elec, Shizuoka Univ.¹, JAIST², Faculty of Physical and Applied Sciences³)

1:45 PM - 2:00 PM

▲ [20p-C8-3] Ab - initio study of interactive-donor states of multiple P-atoms in Si nanoplates

^○Le The Anh¹, Arup Samanta², Daniel Moraru², Takeshi Mizuno², Manoharan Muruganathan¹, Michiharu Tabe², Hiroshi Mizuta^1,3 (JAIST¹, Shizuoka Univ.², Univ. of Southampton³)

2:00 PM - 2:15 PM

[20p-C8-4] Transport via dopant-quantum-dots fabricated by thermal diffusion through nano-masks

^○(P)Daniel Moraru¹, Arup Samanta¹, Le The Anh², Takeshi Mizuno¹, Hiroshi Mizuta^2,3, Michiharu Tabe¹ (Shizuoka Univ., RIE¹, JAIST², Univ. Southampton³)

2:15 PM - 2:30 PM

▲ [20p-C8-5] Observation of Individual Dopants in the Electrical Characteristics of Nanoscale pn Junctions

^○(D)Sri Purwiyanti^1,2, Daniel Moraru¹, Takeshi Mizuno¹, Djoko Hartanto², Michiharu Tabe¹ (Research Inst. of Elec., Shizuoka Univ.¹, Dep. of Elec., UI²)

Sessions

13. Semiconductors A (Silicon) » 13.6 Silicon devices / Integration technology

[18p-P10-1~13] 13.6 Silicon devices / Integration technology

△ [18p-P10-2] Ultra-thin body Ge-on insulator nMOSFETs fabricated by Ge condensation and Sb diffusion

▲ [18p-P10-13] A DC-27 GHz -30 dB Isolation Tx/Rx Single Pole Double Throw (SPDT) Switch for Gaussian Monocycle Pulse Transmission

[19a-C8-1~12] 13.6 Silicon devices / Integration technology

△ [19a-C8-4] A Study on Strain Induced Random Telegraph Noise Suppression in pMOSFETs

△ [19a-C8-5] Dependence of soft error rate in SOI SRAM on generated charge under buried oxide by high energy ion probes

▲ [19a-C8-8] Recovery Behaviors of |Vth| Shift of pFETs by High-Voltage OFF-State and ON-State Stress for Post-Fabrication SRAM Cell Stability Self-Improvement

▲ [19a-C8-10] Performance Degradation Due to Drain-Induced Barrier Lowering in Ultra-Low Supply Voltage CMOS Circuits Operating in Subthreshold Region

[19p-C8-1~18] 13.6 Silicon devices / Integration technology

△ [19p-C8-2] Characterization of MOS Si/SiGe quantum point contact

△ [19p-C8-3] Characterization of p-Channel Si Double Quantum Dot by Hole Transport

△ [19p-C8-4] Observation of the excitation of electrons in silicon quantum dots generated from the back-action of a charge sensor

△ [19p-C8-5] Charge sensing of a silicon triangular triple quantum dot system

△ [19p-C8-12] Low temperature formation of Ni-GaSb alloy Schottky junction for Metal Source/Drain of GaSb pMOSFET

△ [19p-C8-13] Channel Length Scaling Limits of III-V Channel MOSFETs Governed By Source-Drain Direct Tunneling

[20a-C8-1~12] 13.6 Silicon devices / Integration technology

△ [20a-C8-3] Investigation of Mechanical-Stress Reduction in 3D IC with Room Temperature Curing Adhesive

▲ [20a-C8-9] Analysis of Photoresponse in SOI FinFET

[20p-C8-1~5] 13.6 Silicon devices / Integration technology

▲ [20p-C8-1] KFM Measurement of Nano-Scale Selectively Doped Silicon Channel

▲ [20p-C8-2] Transport Spectroscopy of Dopant States in Randomly-Doped Single-Electron Transistors

▲ [20p-C8-3] Ab - initio study of interactive-donor states of multiple P-atoms in Si nanoplates

▲ [20p-C8-5] Observation of Individual Dopants in the Electrical Characteristics of Nanoscale pn Junctions