[19a-C8-1~12] 13.6 Silicon devices / Integration technology

▲ [19a-C8-10] Performance Degradation Due to Drain-Induced Barrier Lowering in Ultra-Low Supply Voltage CMOS Circuits Operating in Subthreshold Region

^○SeungMin Jung¹, Tomoko Mizutani¹, Toshiro Hiramoto¹ (IIS, Univ. of Tokyo¹)

Keywords:Low power CMOS,Drain-induced barrier lowering