The 61st JSAP Spring Meeting, 2014

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Oral presentation

13. Semiconductors A (Silicon) » 13.3 Si Process・Interconnect・MEMS・Integration

[18a-E14-1~10] 13.3 Si Process・Interconnect・MEMS・Integration

Tue. Mar 18, 2014 9:00 AM - 11:45 AM E14 (E302)

11:30 AM - 11:45 AM

△ [18a-E14-10] 3D CMOS Device by Using Wafer-level 3D Integration Technology

○Mayu Aoki1, Futoshi Furuta1, Kazuyuki Hozawa1, Yuko Hanaoka1, Kenichi Takeda1 (Hitachi1)

Keywords:TSV,三次元実装,ウェハ積層