[18p-E14-1~21] 13.3 Si Process・Interconnect・MEMS・Integration

[18p-E14-1] Strain Distributions at Edge of Corner in Bonded Si in Chip-On-Wafer Structures

^○Noriyuki Taoka¹, Osamu Nakatsuka¹, Mizushima Yoriko^2,3, Hideki kitada^2,3, Kim Young Suk³, Tomoji Nakamura², Takayuki Ohba^3,4, Shigeaki Zaima¹ (Nagoya Univ.¹, Fujitsu Lab.², Tokyo Inst. Tech.³, The Univ. of Tokyo⁴)

Keywords:Chip-on-Wafer,strain,3D