[19p-E14-1~21] 13.3 Si Process・Interconnect・MEMS・Integration

[19p-E14-21] Development of a 3D-IC Tester for Minimal 3D-IC Fab

^○Naoya Watanabe¹, Kenji Kawano², Michiyuki Eto², Shiro Hara¹, Masahiro Aoyagi¹ (AIST¹, STK Technology²)

Keywords:3次元集積回路,ミニマルファブ,テスター