[19p-PG3-1~32] 13.3 Si Process・Interconnect・MEMS・Integration

△ [19p-PG3-13] Self-Aligned Four-Terminal Planar Metal Double-Gate Low-Temperature Poly-Si TFTs on Glass Substrate

^○Shinya Kamo¹, Risa Kurosu¹, Tadashi Sato², Akito Hara¹ (Tohoku Gakuin Univ.¹, RNBS Hiroshima Univ.²)

Keywords:TFT,poly-Si,半導体