[19p-PG3-1~32] 13.3 Si Process・Interconnect・MEMS・Integration

[19p-PG3-31] Decrease of parasitic capacitance by deep mesa etching on SAB based Si/Si junctions

^○Koji Takemura¹, Masashi Morimoto¹, Syota Nishida¹, Jenbo Liang¹, Naoteru Shigekawa¹ (Osaka City Univ.¹)

Keywords:半導体