11:45 AM - 12:00 PM
▲ [8a-C18-11] Variability Characterictics of Gate-All-Around Polycrystalline Silicon Nanowire Transistors with 10nm-Scale Width
Keywords:Gate-All-Around, Polycrystalline Silicon Nanowire, Variability Characterictics
[Introduction] Poly-Si nanowire (NW) transistors have attracted attention for 3D multilayer stack integrated circuits and NAND flash memory applications [1]. Most of reported poly-Si NW transistors have width larger than 30nm but few transistors with width of 10nm scale have been reported. In this work, GAA poly-Si NW transistors with 10nm scale width have been fabricated in very controllable manner using electron-beam (EB) lithography. The variability characteristics of threshold voltage (Vth) and drain current (Id) are evaluated [2].
[Fabrication] The EB conditions were carefully optimized so that the actual NW width just after RIE (before gate oxidation) is the same as design width (Wd). Fig. 1 shows cross-section TEM images of a fabricated NW transistor. The trapezoid-shaped GAA structure is confirmed. The width of top and bottom are ~5nm and 15nm, respectively.
[Results] Fig. 2 shows I-V characteristics of a planar transistor and the NW transistor (Wd=15nm, L=300nm, the specific transistor whose cross-section is shown in Fig. 1). In the NW transistor, electrical properties are improved because the total number of grain boundaries and traps are reduced by scaling poly-Si film. Fig. 3 shows variability characteristics. To make a fair comparison with reported data [3], the Pelgrom plot is shown in Fig. 4. σVth/Tinv is evaluated to cancel the effect of Tinv for Vth variability [3] and overdrive voltage (Vg–Vth) is fixed for Id variability [3]. Smaller or comparable variability than that of reported poly-Si NW transistors [3] is confirmed.
[Summary] GAA Poly-Si NW transistors with width of 10 nm scale were fabricated under precise width control and small variability is confirmed.
[Fabrication] The EB conditions were carefully optimized so that the actual NW width just after RIE (before gate oxidation) is the same as design width (Wd). Fig. 1 shows cross-section TEM images of a fabricated NW transistor. The trapezoid-shaped GAA structure is confirmed. The width of top and bottom are ~5nm and 15nm, respectively.
[Results] Fig. 2 shows I-V characteristics of a planar transistor and the NW transistor (Wd=15nm, L=300nm, the specific transistor whose cross-section is shown in Fig. 1). In the NW transistor, electrical properties are improved because the total number of grain boundaries and traps are reduced by scaling poly-Si film. Fig. 3 shows variability characteristics. To make a fair comparison with reported data [3], the Pelgrom plot is shown in Fig. 4. σVth/Tinv is evaluated to cancel the effect of Tinv for Vth variability [3] and overdrive voltage (Vg–Vth) is fixed for Id variability [3]. Smaller or comparable variability than that of reported poly-Si NW transistors [3] is confirmed.
[Summary] GAA Poly-Si NW transistors with width of 10 nm scale were fabricated under precise width control and small variability is confirmed.