〇Yuta Nakajima^1,2, Noriyuki Uchida², Ryuto Machida¹, Hiroki Fujishiro¹, Junichi Hattori², Kouichi Fukuda², Tatsurou Maeda^1,2 (1.Tokyo University of Science, 2.AIST)

11:45 AM - 12:00 PM

▲ [8a-C18-11] Variability Characterictics of Gate-All-Around Polycrystalline Silicon Nanowire Transistors with 10nm-Scale Width

〇Kihyun Jang¹, Takuya Saraya¹, Masaharu Kobayashi¹, Naomi Sawamoto², Atsushi Ogura², Toshiro Hiramoto¹ (1.The University of Tokyo, 2.Meiji University)

12:00 PM - 12:15 PM

△ [8a-C18-12] Correspondence between Grain Boundary Structures and Transistor Characteristics in Individual Poly-Si Nanowire TFTs Revealed by Analysis of Massive NBD Maps

〇Takanori Asano¹, Riichiro Takaishi¹, Minoru Oda¹, Kiwamu Sakuma¹, Masumi Saitoh¹, Hiroki Tanaka¹ (1.Toshiba corp.)

Oral presentation

[8p-C18-1~8] 13.5 Semiconductor devices and related technologies

6.1と13.3と13.5のコードシェアセッションあり

Fri. Sep 8, 2017 1:45 PM - 4:00 PM C18 (C18)

Yasuo Takahashi(Hokkaido Univ.)

△：奨励賞エントリー
▲：英語発表
▼：奨励賞エントリーかつ英語発表
空欄：どちらもなし

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1:45 PM - 2:00 PM

[8p-C18-1] Spike-Timing-Dependent synaptic Plasticity (STDP) of metal-oxide devices for brain-inspired learning LSIs

〇Takao Marukame¹, Reika Ichihara¹, Kumiko Nomura¹, Shin-ichi Yasuda¹, Yuichiro Mitani¹ (1.Toshiba corp.)

2:00 PM - 2:15 PM

[8p-C18-2] Evaluation of analog memory characteristics of FeFET for Time-domain weighted-sum calculation

〇Masataka Harada¹, Takashi Morie¹, Mitsue Takahashi², Shigeki Sakai² (1.Kyushu Inst. Tech, 2.AIST)

2:15 PM - 2:30 PM

[8p-C18-3] Stability analysis of neuron circuits using VO₂ metal-insulator transition

〇Takeaki Yajima¹, Tomonori Nishimura¹, Akira Toriumi¹ (1.Univ of Tokyo)

2:30 PM - 2:45 PM

[8p-C18-4] Fabrication of Ag-Ag₂S core-shell nanoparticles and its electrical properties

〇Yurina Amamoto¹, Hadiyawarman .¹, Tanaka Hirofumi¹ (1.Kyushu Inst. Tec.)

3:00 PM - 3:15 PM

[8p-C18-5] Resistive Switching Characteristics of CeO_x/SiO₂ with La₂O₃ Capping Layer

〇Kazuto Mizutani¹, Iriya Muneta¹, Takuya Hoshii¹, Hitoshi Wakabayashi¹, Kazuo Tsutsui², Hiroshi Iwai², Kuniyuki Kakushima¹ (1.Tokyo Tech, 2.Tokyo Tech. IIR)

3:15 PM - 3:30 PM

[8p-C18-6] Electrical characteristics of CeO_x MIM capacitors

〇Yoshitaka Takaku¹, Iriya Muneta¹, Takuya Hoshii¹, Hitoshi Wakabayashi¹, Kazuo Tsutsui¹, Hiroshi Iwai², Kuniyuki Kakushima¹ (1.Tokyotech, 2.Tokyotech IIR)

3:30 PM - 3:45 PM

[8p-C18-7] Error Recovery Effect and High Reliable Method for Endurance in TaO_x ReRAM

〇(M1C)Shouhei Fukuyama¹, Maeda Kazuki¹, Takeuchi Ken¹ (1.Chuo Univ.)

3:45 PM - 4:00 PM

[8p-C18-8] Static-power reduction ability of nonvolatile SRAM with magnetic tunnel junctions

〇Daiki Kitagata¹, Shuu'ichirou Yamamoto¹, Satoshi Sugahara¹ (1.FIRST, Tokyo Inst. of Tech.)

Poster presentation

[7a-PB3-1~9] 13.5 Semiconductor devices and related technologies

Thu. Sep 7, 2017 9:30 AM - 11:30 AM PB3 (P)

△：奨励賞エントリー
▲：英語発表
▼：奨励賞エントリーかつ英語発表
空欄：どちらもなし

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9:30 AM - 11:30 AM

[7a-PB3-1] Extremely-thin-body strained GOI pMOSFETs fabricated by thinning Ge condensation GOI through plasma oxidation

〇(D)Wukang Kim¹, Mitsuru Takenaka¹, Shinichi Takagi¹ (1.The Univ. of Tokyo)

9:30 AM - 11:30 AM

▼ [7a-PB3-2] Effect of SiGe Layer Thickness in Starting Substrate on Electrical Properties of Ultrathin Body Ge-on-Insulator pMOSFET fabricated by Ge condensation

〇(DC)KwangWon Jo¹, WuKang Kim¹, Mitsuru Takenaka¹, Shinichi Takagi¹ (1.The Univ. of Tokyo, Department of Electrical Engineering and Information Systems)

9:30 AM - 11:30 AM

▲ [7a-PB3-3] Effects of gate electrode metal and drain doping concentration on electrical characteristics of Ge/Si hetero-junction tunneling FETs

〇(D)TaeEon Bae¹, Ryota Suzuki¹, Ryosho Nakane¹, Mitsuru Takenaka¹, Shinichi Takagi¹ (1.The Univ. of Tokyo)

9:30 AM - 11:30 AM

[7a-PB3-4] Electric Characteristic of Junctionless FET or Intrinsic FET Embedding Gold Nanoparticles

〇Takahiko Ban¹, Shinji Migita², Ichiro Yamashita³, Yukiharu Uraoka³, Shin-ichi Yamamoto¹ (1.Ryukoku Univ., 2.AIST, 3.NAIST)

9:30 AM - 11:30 AM

[7a-PB3-5] Compact model of FeFET taking account the thermal flip of multi-domain polarization

〇Hidehiro Asai¹, Koichi Fukuda¹, Mitsue Takahashi¹, Shigeki Sakai¹ (1.AIST)

9:30 AM - 11:30 AM

[7a-PB3-6] Surface activated bonding of LiNbO₃ wafer and SiO₂ wafer with low-temperature heat-treatment

〇Ryo Takigawa¹, Eiji Higurashi^2,3, Tanemasa Asano¹ (1.Kyushu Univ., 2.AIST, 3.The Univ. of Tokyo)

9:30 AM - 11:30 AM

[7a-PB3-7] Electronic transfer sequence of single-common-gate parallel-double-dot single-electron device with asymmetric gate capacitances

〇Yusuke Watanabe¹, Shigeru Imai¹ (1.Ritsumeikan Univ)

9:30 AM - 11:30 AM

[7a-PB3-8] Analysis of soft errors for FinFET technology based on the multiple sensitive volume model using PHITS code

〇Shinichiro Abe¹, Tatsuhiko Sato¹, Takashi Kato², Hideya Matsuyama² (1.JAEA, 2.Socionext Inc.)

9:30 AM - 11:30 AM

△ [7a-PB3-9] Charge-pumping electrically-detected magnetic resonance for detection of silicon dangling bonds

〇Masahiro Hori¹, Toshiaki Tsuchiya¹, Yukinori Ono¹ (1.Shizuoka Univ.)

Sessions

13 Semiconductors » 13.5 Semiconductor devices and related technologies

[8a-C18-1~12] 13.5 Semiconductor devices and related technologies

6.1と13.3と13.5のコードシェアセッションあり

△ [8a-C18-1] Impacts of Device Parameter Values on the Performance of Vertical TFET

△ [8a-C18-2] Consideration on Impacts of Traps on Trap-Assisted-Tunnel Current in Vertical TFET

[8a-C18-3] Influence of Quantum Effect on InGaAs / GaAsSb Double Gate Tunnel FET

[8a-C18-4] Impact of Tunnel FET CV characteristics on inverter circuit performance

[8a-C18-5] Characterization of Hysteresis on Super Steep SS PN-Body Tied FET

[8a-C18-6] Voltage-based Equivalent Circuit Model of MOS-Gated Thyristor for Optimizing Steep Subthreshold Slope PN-Body Tied SOI FET

[8a-C18-7] [JSAP Young Scientist Award Speech] High compressive strain GOI pMOSFET fabricated by Ge condensation process with reduced cooling rate

△ [8a-C18-8] Channel thickness scaling induced electron mobility enhancement in UTB-GeOI

[8a-C18-9] Channel mobility dependence on substrate concentration for metal S/D Ge n-MOSFET

[8a-C18-10] Thermal transport property of NiGe/Ge contact structure

▲ [8a-C18-11] Variability Characterictics of Gate-All-Around Polycrystalline Silicon Nanowire Transistors with 10nm-Scale Width

△ [8a-C18-12] Correspondence between Grain Boundary Structures and Transistor Characteristics in Individual Poly-Si Nanowire TFTs Revealed by Analysis of Massive NBD Maps

[8p-C18-1~8] 13.5 Semiconductor devices and related technologies

6.1と13.3と13.5のコードシェアセッションあり

[8p-C18-1] Spike-Timing-Dependent synaptic Plasticity (STDP) of metal-oxide devices for brain-inspired learning LSIs

[8p-C18-2] Evaluation of analog memory characteristics of FeFET for Time-domain weighted-sum calculation

[8p-C18-3] Stability analysis of neuron circuits using VO₂ metal-insulator transition

[8p-C18-4] Fabrication of Ag-Ag₂S core-shell nanoparticles and its electrical properties

[8p-C18-5] Resistive Switching Characteristics of CeO_x/SiO₂ with La₂O₃ Capping Layer

[8p-C18-6] Electrical characteristics of CeO_x MIM capacitors

[8p-C18-7] Error Recovery Effect and High Reliable Method for Endurance in TaO_x ReRAM

[8p-C18-8] Static-power reduction ability of nonvolatile SRAM with magnetic tunnel junctions

[7a-PB3-1~9] 13.5 Semiconductor devices and related technologies

[7a-PB3-1] Extremely-thin-body strained GOI pMOSFETs fabricated by thinning Ge condensation GOI through plasma oxidation

▼ [7a-PB3-2] Effect of SiGe Layer Thickness in Starting Substrate on Electrical Properties of Ultrathin Body Ge-on-Insulator pMOSFET fabricated by Ge condensation

▲ [7a-PB3-3] Effects of gate electrode metal and drain doping concentration on electrical characteristics of Ge/Si hetero-junction tunneling FETs

[7a-PB3-4] Electric Characteristic of Junctionless FET or Intrinsic FET Embedding Gold Nanoparticles

[7a-PB3-5] Compact model of FeFET taking account the thermal flip of multi-domain polarization

[7a-PB3-6] Surface activated bonding of LiNbO₃ wafer and SiO₂ wafer with low-temperature heat-treatment

[7a-PB3-7] Electronic transfer sequence of single-common-gate parallel-double-dot single-electron device with asymmetric gate capacitances

[7a-PB3-8] Analysis of soft errors for FinFET technology based on the multiple sensitive volume model using PHITS code

△ [7a-PB3-9] Charge-pumping electrically-detected magnetic resonance for detection of silicon dangling bonds

Authentication