The 78th JSAP Autumn Meeting, 2017

Presentation information

Poster presentation

13 Semiconductors » 13.5 Semiconductor devices and related technologies

[7a-PB3-1~9] 13.5 Semiconductor devices and related technologies

Thu. Sep 7, 2017 9:30 AM - 11:30 AM PB3 (P)

9:30 AM - 11:30 AM

[7a-PB3-2] Effect of SiGe Layer Thickness in Starting Substrate on Electrical Properties of Ultrathin Body Ge-on-Insulator pMOSFET fabricated by Ge condensation

〇(DC)KwangWon Jo1, WuKang Kim1, Mitsuru Takenaka1, Shinichi Takagi1 (1.The Univ. of Tokyo, Department of Electrical Engineering and Information Systems)

Keywords:Ge condensation, GOI, Strain

We fabricated 10 nm-thick ultra thin body (UTB) Ge on Insulator (GOI) pMOSFETs with high mobility by using Ge condensation. It is found that higher compressive strain and resulting high hole mobility is obtained for starting substrate of Si/SiGe/SOI with thinner SiGe before the Ge condensation process with 4 hour cooling time.