Consideration on Impacts of Traps on Trap-Assisted-Tunnel Current in Vertical TFET

Yoshiaki Mori; Shingo Sato; Yasuhisa Omura; Abhijit Mallik

Presentation information

Oral presentation

13 Semiconductors » 13.5 Semiconductor devices and related technologies

[8a-C18-1~12] 13.5 Semiconductor devices and related technologies

6.1と13.3と13.5のコードシェアセッションあり

Fri. Sep 8, 2017 9:00 AM - 12:15 PM C18 (C18)

Tomonori Nishimura(Univ. of Tokyo), Takahiro Mori(AIST)

9:15 AM - 9:30 AM

△ [8a-C18-2] Consideration on Impacts of Traps on Trap-Assisted-Tunnel Current in Vertical TFET

〇Yoshiaki Mori¹, Shingo Sato¹, Yasuhisa Omura¹, Abhijit Mallik² (1.Kansai Univ., 2.Univ. of Calcutta)

Keywords:tunnel FET, simulation, Trap assisted tunneling

TFET attracts attention from the view point of low-energy operation and steep swing. In this presentation, we discuss impact of TAT current on OFF and ON characteristcs of VTFET. Simulation results are compared with experimental results, and we address to physical background of phenomea observed in experimental results.