The 78th JSAP Autumn Meeting, 2017

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13 Semiconductors » 13.5 Semiconductor devices and related technologies

[8a-C18-1~12] 13.5 Semiconductor devices and related technologies

6.1と13.3と13.5のコードシェアセッションあり

Fri. Sep 8, 2017 9:00 AM - 12:15 PM C18 (C18)

Tomonori Nishimura(Univ. of Tokyo), Takahiro Mori(AIST)

10:15 AM - 10:30 AM

[8a-C18-6] Voltage-based Equivalent Circuit Model of MOS-Gated Thyristor for Optimizing Steep Subthreshold Slope PN-Body Tied SOI FET

〇(M2)DAIKI UEDA1, KIYOSHI TAKEUCHI1, MASAHARU KOBAYASHI1, TOSHIRO HIRAMOTO1 (1.IIS, Univ. of Tokyo)

Keywords:Steep Subthreshold Slope, PN-Body Tied SOI FET, MOS-Gated Thyristor