Naoya Watanabe

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Speaker, Author, Co-Author

Tue. Mar 14, 2017 1:30 PM - 3:30 PM P3 (BP)

Poster presentation
| 13 Semiconductors
| 13.4 Si wafer processing /Si based thin film /Interconnect technology/ MEMS/ Integration technology

[14p-P3-1~19] 13.4 Si wafer processing /Si based thin film /Interconnect technology/ MEMS/ Integration technology

1:30 PM - 3:30 PM

[14p-P3-7] TSV Bottom Cleaning Process for High Yield Formation of Via-Last TSVs

〇Naoya Watanabe¹, Kikuchi Kikuchi², Azusa Yanagisawa², Haruo Shimamoto¹, Katsuya Kikuchi¹, Masahiro Aoyagi¹, Akio Nakamura² (1.AIST, 2.LAPIS Semiconductor)

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